Inductances have been widely used in the semiconductor chip technology with the intent of extending the amplification band and compensating transmission characteristics in high-speed communication circuits. However, a conventional on-chip inductor fabricated using metal wiring layers, such as passive spiral inductors, not only requires large real estate and consumes high power, but has relatively low quality factor Q due to undesirable resonance caused by parasitics existing in a CMOS substrate. As a result, the cost to fabricate a conventional inductor is high due to the increased chip size. Recently, active inductors (AI) have been applied to substitute passive spiral inductor in some CMOS RF circuits because of their miniaturized size, lower power consumption, less cross-talk, lower cost, higher Q, and fabrication processes that is fully compatible with base CMOS technologies. In general, an active inductor is a CMOS circuit having inductor-like output impedance, and consists of active CMOS transistors, resistors and capacitors. Such devices have found wide application in CMOS RF circuits, such as MMIC, RF filter, matching network, LC circuits, and the like.
In U.S. Pat. No. 7,049,888 issued to Masaaki Soda, a CMOS circuit is described having output voltage and current characteristics equivalent to those of an inductor. Since active inductors are significantly smaller in size than conventional spiral inductors of equivalent inductance value, the circuit size decreases significantly.
Another illustrative example is reported by K. H. Chiang, et al., in a paper titled “A Modular Approach for High Q Microwave CMOS Active Inductor Design” published in the Proceedings of the 7th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, pp. 41-44. Therein, a modular approach to an L-band CMOS Active Inductor is described and is designed based on a series of conventional low Q-factor gyrator-C basic modules. In the design, the inductor elements are connected in a serial arrangement, as stated in the aforementioned paper: “when the modular series connection changes from N=1 to 3, the value of Q-factor can be tuned from 11.8 to 972.” In order words, the serial connection is mainly intended to boost Q even though its total inductance does not increase monotonically with the number of modular active inductors. The design, however, is not intended for connecting AI elements in parallel or in series, and displays a behavior similar to conventional inductive elements.
In today's ASIC environment of designing highly integrated chips, such as SOC, high-speed I/Os and/or analog communication macros, inductors having various sizes are often needed. The RF industry has a particular interest in inductors with array or modular configuration which gives designers much needed flexibility to optimize circuit performance over a wide range of applications and frequencies, while keeping at the same time the circuitry at a minimum size and cost. One can, of course, build many active inductor circuits of various sizes to meet this requirement, but the drawback is that each circuit has to be characterized and individually tuned to obtain the correct inductance value. At the end, the size of the circuit and the cost for tuning becomes impractical.
In related prior art U.S. Pat. No. 6,737,944 issued to Kunikiyo, there is described an active inductor formed by two field effect transistors, having the drain of the first field effect transistor coupled to the source of the second field effect transistor, the gate of the first field effect transistor coupled to the drain of the second field effect transistor with no active element interposed therebetween. The active inductor also includes a feedback path between the source of the first field effect transistor and the gate of the second field effect transistor. The gate and source of the second field-effect transistor serve as two ports of the active inductor. The AI described is mainly intended to reduce the series resistance component of the inductor to reduce power consumption, minimize the loss and provide the inductance over a wide bandwidth.
Generally, conventional AIs tend to gravitate toward a customized design, i.e., a design tailored to create an inductor having a specific Q value.
The manufacture references of the proposed active inductor structure are prior art embedded-DRAM (eDRAM) on either bulk silicon substrates or SOI (silicon-on-insulator) substrates. For example, bulk eDRAM processes have been described, e.g., in U.S. Pat. No. 6,261,894 issued to Mandelman et al., and in a Conference report titled “Device Equivalent of Logic Performance in 0.18 um and Extension to 0.13 um Embedded DRAM Technology”, published in the Proceedings of the International Symposium on VLSI Technology, System, and Application (2001). Another example of a prior art fabrication of an SOI eDRAM is described in U.S. Pat. No. 7,129,130, issued to Adkisson et al. All of the aforementioned eDRAMs disclose active device processes and structures with an integrated deep-trench capacitor in close vicinity which can be applied to the active inductor.